If you follow Micron because you invest in memory, advise its competitors, or run an IP team in the industry, the headline number is no longer the $445 million verdict Netlist won against Micron in 2024. The next headline could come from a second case Netlist filed in May 2025, built on a brand-new patent Netlist alleges covers the design of the stacked memory chips Micron uses in its High Bandwidth Memory (HBM) products. HBM is the memory inside the AI accelerators NVIDIA is building today.

The new patent is U.S. Patent No. 12,308,087 ("the '087"), issued to Netlist on May 20, 2025. Within the same month, Netlist filed in the Eastern District of Texas, alleging that the '087 covers Micron's HBM products; the case is captioned Netlist, Inc. v. Micron Technology, Inc., Case No. 2:25-cv-00558.¹ In July 2025, Netlist amended the complaint to add U.S. 10,025,731 (targeting Micron's DDR5 server memory modules) and to name Avnet, one of Micron's distributors, as a co-defendant. On March 6, 2026, the case moved from Texas to the District of Delaware on Micron's motion.

A small note on the filing date: Netlist's SEC filings list May 20, 2025; Micron's list May 19, 2025. The most likely explanation is a late-day court filing recorded slightly differently by each side. The substance is the same.

The '087 is not part of the same patent family as the patents in the original $445M case. It is separately issued, and its claims are directed to the architecture of stacked-die memory, the same broad category HBM belongs to. The result is a second front in the Netlist/Micron dispute, on a much larger commercial base. Whether the '087 ultimately reads on any Micron product is a question for the court.

This article does three things, in plain English:

1. Explains what the '087 patent actually covers, and why HBM products (including Micron's HBM4) appear to be the natural commercial target of an assertion in this space.
2. Shows where Micron sits versus Samsung and SK Hynix in active Patent Office workload, which can serve as a proxy for legal-team capacity.
3. Lays out three concrete moves memory IP teams may want to consider this quarter.

What the '087 Patent Covers, and Why HBM4 Appears to Be the Commercial Target

The patent's core invention, as described in the specification, is a specific engineering choice for how to send signals to memory chips that are stacked on top of each other.

A bit of background: modern HBM products stack many DRAM chips on top of each other to fit more memory in less space. The chips are connected by tiny vertical wires called "through-silicon vias" (TSVs for short) that run straight through the silicon. Micron's current HBM4 product stacks 12 chips together (the 36GB 12H model), and Micron is also sampling a 16-chip stack (the 48GB 16H).⁵

The technical problem the '087 addresses: when 12 chips are stacked, the chip at the top sees a very different electrical load than the chip at the bottom, because the signal has to travel through a longer chain of TSVs to reach it. If you use identical signal drivers (the circuits that push data onto the wires) for every chip in the stack, the signal reaching the top chip is weaker and noisier than the signal reaching the bottom chip. That hurts reliability and speed.

The '087's idea is to use different-sized drivers for different chips in the stack, with bigger drivers for chips that are further away (and see more load) and smaller drivers for chips closer in. The patent's main claim spells that out:

The first part of the claim describes stacked DRAM with separate data paths per chip; that high-level description appears to fit the general architecture of HBM products on the market. The deciding element, the one Netlist would need to establish against Micron's HBM4 in court, is the final line: different driver sizes for different chips in the stack.

Variable driver sizing is not the only way to solve the stacked-chip signal problem. Engineers also use techniques like active signal equalization, programmable drive-strength compensation, and termination resistors at the TSV connections. The fact that variable driver sizing is widely known among memory engineers in 2026 does not, by itself, render the '087 invalid. For an invalidity argument to succeed, Micron would generally need to identify a publication from before November 3, 2010 (the '087's priority date) that anticipates or renders obvious the claimed combination.

Micron's three lines of defense

Micron has three independent arguments available, and the strongest legal posture combines all three.

Defense 1. Argue the patent's words don't cover what Micron makes. This kind of argument turns on how the court interprets specific words in the patent. Two phrases in claim 1 are open to dispute:

• "DRAM package" (an HBM stack includes a base logic chip alongside the DRAM chips). Does that combination count as a single "DRAM package" in the patent's language, or as something else?
• "Different driver size" (does any kind of difference in how Micron tunes its drivers chip-by-chip count, or does the patent require physically different driver circuits?)

Defense 2. Argue the facts. Micron's drivers aren't actually different sizes between chips. Even if a court reads the patent broadly, Micron can argue that, as an engineering matter, its HBM4 simply doesn't do what the patent describes, and that Micron solves the signal problem some other way (for example, by equalizing signals at the base logic chip, or by using programmable drive strength). This question gets resolved by engineering documentation produced during discovery.

Defense 3. Identify prior art predating November 3, 2010 that could support an invalidity challenge. Two publicly available references appear relevant as starting anchors for that research, though neither has yet been the subject of a published limitation-by-limitation analysis against claim 1 of the '087:

• Elpida Memory (a Japanese DRAM maker Micron later acquired in 2013) announced a copper-TSV 8-gigabit DRAM on August 27, 2009, described as an eight-chip stack with 1,030 vertical connections between layers, in working silicon. The original Elpida press release is no longer online (the company's website went down after the Micron acquisition), but the announcement is archived at Phys.org and Semiconductor Digest.⁷
• Tezzaron Semiconductor's wafer-stacking work was publicly described in May 2005, in a 3D processor with stacked memory built from two face-to-face bonded silicon wafers (archived at the industry news site Design-Reuse).⁸

Both publications are relevant prior-art anchors for the broad architectural setting of claim 1 (stacked DRAM with vertical interconnects). Whether either, alone or in combination with other prior art, discloses every structural limitation of claim 1, and in particular the variable driver sizing limitation, would require a careful limitation-by-limitation analysis and likely expert testimony. The next layer of potentially relevant prior art lives in the academic record (ISSCC and VLSI Symposium proceedings from 2008 through 2010 on signal integrity in stacked memory) and in the JEDEC standards-body archives from the same period.

One useful piece of background: the '087 issued from a longer Netlist patent family. The original application (No. 17/694,649, filed March 2022) was a continuation of earlier Netlist patents. The application's file wrapper at the USPTO Patent Center shows how the driver-sizing language was narrowed over three years of negotiation. That history matters for two reasons. First, it may sharpen the obviousness argument by showing what Netlist conceded was already known. Second, under the doctrine of prosecution-history estoppel, a patentee generally cannot later claim coverage of subject matter it gave up to obtain the grant.

Where Micron Sits Versus Samsung and SK Hynix on Active Patent Office Work

Every patent application in front of the US Patent Office goes through a series of back-and-forth exchanges with an examiner. Each official challenge from the examiner is called an "Office Action" (OA), and each requires a written response from the company's patent lawyers. The number of open Office Actions a company is carrying at any given moment can be a useful proxy for how stretched its legal team is, though the relationship varies by company structure and outside-counsel mix. When a company is also defending litigation, that capacity matters operationally.

The IP Author platform ranks the top 50 US patent assignees by open Office Actions, refreshed daily from USPTO records. Micron sits at #26 with 415 open OAs as of May 22, 2026.² The peer set is more useful than the absolute number:

Among the three companies that dominate HBM supply, the workload is uneven. Samsung's 2,336 is large in part because Samsung is a conglomerate; its patent filings cover displays, foundry services, and consumer electronics, not memory alone. The cleaner comparison for portfolio managers may be Micron versus SK Hynix in the memory space:

Micron carries roughly 1.8× SK Hynix's active US patent workload at the Patent Office. The data suggests this matters operationally, because the lawyers handling those Office Actions often overlap with the lawyers responding to new litigation. A stretched team going into a major lawsuit faces real capacity strain.

What the headline 415 number does not show (but the platform does) is where Micron's workload concentrates by examiner, and which examiners historically respond best to interviews versus written-only responses. A couple of practical notes on reading the platform's data:

• The highest "interview-lift" figures on Micron's docket today happen to sit on very small case counts (1 or 2 cases). Those numbers are per-case flags, not reliable portfolio statistics. A single case can't tell you much about the population.
• The examiners with larger Micron caseloads and steady single-digit-to-mid-teens interview-lift figures are where the signal becomes reliable enough for portfolio-scale decisions. Both columns are surfaced on the platform; which one to use depends on the question being asked.

The full top-15 examiner table for Micron is at insights.ipauthor.com/company/micron-technology-inc.html.

The $445M Verdict, the Appeal That Closed, and the New Case

In May 2024, a federal jury in Eastern District of Texas found that Micron willfully infringed two earlier Netlist patents (U.S. 7,619,912 and U.S. 11,093,417) and awarded Netlist $425 million on the first patent and $20 million on the second, for a total of $445 million.³ Micron's post-trial motions were denied in June 2025. Micron then appealed and separately challenged the patents at the Patent Trial and Appeal Board (PTAB), the USPTO's tribunal for deciding patent challenges.

On February 20, 2026, the U.S. Court of Appeals for the Federal Circuit (the appeals court for patent cases) ruled against Micron's challenges and affirmed the lower court. (Micron Technology, Inc. v. Netlist, Inc., Appeal No. 24-1312, nonprecedential.⁴) The willfulness finding stands. Because willful infringement allows the trial judge to enhance damages up to threefold under 35 U.S.C. §284, potential exposure on those two patents alone could exceed the $445M jury award.

But months before that appeal ruling, Netlist had already opened the second front. In May 2025, the same month the '087 issued, Netlist filed the new complaint in Texas (Case No. 2:25-cv-00558), asserting the '087 against Micron's HBM. The July 2025 amendment added the '731 patent (directed to Micron's DDR5 modules) and brought Avnet in. The case transferred to Delaware on March 6, 2026.

Why the commercial stakes appear larger this time

Micron's HBM4 is in volume production for NVIDIA's next-generation "Vera Rubin" AI platform.⁵ Yole Group projects the global HBM market at $98 billion by 2030, up from $17 billion in 2024 (a 33% CAGR).⁶ Micron's share has been growing: TrendForce reported Micron at 7% in 2024 and targeting 24% by year-end 2025.⁶

The '087 does not expire until November 2031. A few clarifying points for investors:

• The Yole figure is global; US patent damages are calculated only against US-attributable sales of the accused product.
• HBM is a component Micron sells to NVIDIA, which then puts it into GPUs that ship worldwide. The damages base depends on how the court treats HBM units in NVIDIA's US-based manufacturing versus its overseas operations.
• Either way, the base is orders of magnitude larger than the DDR-module sales in the 2024 case, and grows every quarter HBM4 ships in volume.

What Memory Companies Should Be Doing This Quarter

1. 1

   Map your shipping memory products against Netlist's entire US patent portfolio, not just the patents Netlist has already asserted.

   Netlist's recent pattern appears consistent: it asserts whatever is ready to litigate, then amends complaints as new related patents issue, generally targeting the biggest revenue product line. The '087 issued on May 20, 2025 and was in the complaint within the same month. Any memory or memory-adjacent company may benefit from being able to answer, in about 15 minutes: "Which Netlist patent appears most likely to be asserted next, against which of our products?", including against patents still pending at the Patent Office. Pending continuations could implicate the same risk surface.

2. 2

   Treat prior-art research as an ongoing capability, not a one-time project.

   The '087 priority date is November 3, 2010. The strongest invalidity arguments are likely to live in narrow pre-2010 technical publications and JEDEC standards-body working materials, not in surface-level keyword searches. That research can take 6 to 12 months to do well, and generally has to start before a lawsuit lands, not after. Files documenting a structured research process (explicit search terms, database scope, and reasoning behind each cited reference) tend to hold up better at the PTAB and the Federal Circuit than files built from keyword hits.

3. 3

   Document now what your engineering and licensing teams knew, and when.

   The Federal Circuit's willful-infringement affirmance against Micron is a calibration point. The data suggests juries may credit "should have known" arguments in the memory industry, where JEDEC committee participation, OEM purchase inquiries, and licensing letters all leave a paper trail that could establish notice. Building documentation now, in a form that survives discovery, is more defensible than building it after a complaint arrives. (Reminder: a willfulness finding allows the judge to enhance damages up to threefold.)

The Bottom Line

The $445 million verdict was the prologue. The next chapter turns on the '087, a single Netlist patent issued in May 2025 and asserted in court within the month. The patent is narrow enough to turn on one specific engineering choice (variable-sized drivers for stacked DRAM chips), yet its independent claim could potentially be read to reach the broader architecture of stacked-die memory products, including HBM. Whether it actually reads on any Micron product is a question for the court. Memory companies, and the IP teams advising them, that can answer in real time "Where is our potential exposure on stacked-die driver design? What is the other side likely to assert next? Where is our prior-art evidence?" are likely to spend less in 2027 than teams that wait for the next complaint to force the analysis.